1. Field of the Invention
The present invention relates to a phase-locked loop circuit and a delay-locked loop circuit, for example, and relates to a phase-locked loop circuit and a delay-locked loop circuit in a digital television set for generating dot clocks.
2. Description of the Related Art
For displaying a video signal on a display of a personal computer or for displaying OSD (on screen display) text on a television monitor, use is made of dot clocks obtained by multiplication by a PLL (phase-locked loop) circuit using the horizontal synchronization signal HSYNC as a reference clock signal. If the jitter of the PLL circuit is large, flicker or waving will appear on the screen and will end up being caught visually, so a PLL circuit having low jitter is considered necessary for a dot clock generating circuit.
A change of voltage conditions slower than the reference clock signal or the natural frequency of a PLL circuit is corrected by the feedback loop of the PLL circuit itself. However, digital noise generated in shorter periods than that of the reference clock signal can be considered as random components in each cycle of the reference clock signal and cannot be corrected sufficiently by the feedback loop, thus causing jitter after the PLL is locked.
For random jitter occurring after the PLL is locked and seldom lasting long, rather than causing a change of the frequency mainly by frequency pull-in through charging or discharging a capacitor of a loop filter, it is effective to correct the phase of jitter portion in each cycle mainly by phase pull-in performed in each cycle of the reference clock signal. However, since the change of the voltage of the pulse signal input to a VCO circuit cannot be made too large during phase pull-in, it is difficult to design the circuit to correct exactly 100% of the jitter by the phase pull-in alone. Therefore, it is thought optimal to use the method of digitally correcting the phase of jitter when generating dot clocks together with phase correction by phase pull-in of a PLL circuit. For example, the phase of the jitter is corrected by selecting the clock rising earliest from a trailing edge (the left end of the screen) of the horizontal synchronization signal HSYNC from a plurality of clocks different in phase and using this clock to generate dot clocks.
When correcting the phase mainly by phase pull-in, a lag-lead filter is suitable for the loop filter in a PLL circuit or a DLL (delay-locked loop). A lag-lead filter is for example a filter comprised of a series circuit of a resistor and capacitor and has a phase property of a phase delayed at a low band being restored at a high band.
When using a lag-lead filter as a loop filter, a control voltage is generated having a combined waveform of a rectangular waveform corresponding to pulse signals output by a phase comparator (up signal and down signal) and a flat waveform along a time axis generated by the charging and discharging of a capacitor by a charge pump circuit. In the rectangular waveform, phase pull-in is mainly performed, while in the flat waveform along the time axis, frequency pull-in together with indirect phase pull-in is performed. Due to this, a larger phase pull-in can be obtained compared with the case of using a lag filter in which the waveform is blunted at the high band, so the output current of the charge pump can be designed to be small and the change of a control voltage due to charging and discharging of the capacitor of a loop filter becomes small. As a result, the change of the control voltage after phase pull-in due to a control voltage having a rectangular waveform can be made smaller, and the jitter of frequency can be made smaller.
In addition, by comparing phases at the rising edge (the right end of a screen) of a horizontal synchronization signal HSYNC, since the charge pump circuit is operating in the blanking period, the large change of the clock phase that occurs when using a lag-lead filter does not affect the display on the screen. Furthermore, after the operation of the charge pump circuit is finished and the control voltage becomes sufficiently stable, by digitally correcting the phase of the jitter and generating dot clocks at a trailing edge (the left end of a screen) of the horizontal synchronization signal HSYNC, a picture having little flicker and waving can be obtained.
However, when a low-pass filter is provided after the lag-lead filter to reduce the influence of noise or when a capacitor is provided to stabilize the control voltage between an output of a bias circuit and a ground line or a power line, the rectangular waveform of the control voltage of a voltage controlled oscillator or a voltage controlled delay circuit ends up being blunted. Due to this, the change of the control voltage does not end even after the trailing edge (the left end of the screen) of the horizontal synchronization signal HSYNC, so the phase ends up changing. Therefore, there is a disadvantage that the effect of digital phase correction ends up declining at the trailing edge of the horizontal synchronization signal HSYNC, and the merit of using a lag-lead filter is lost.
Below, a detailed explanation will be made of the above problem in a PLL circuit of the prior art using a lag-lead filter.
FIG. 11 is a view of the configuration of a first mode of a PLL circuit of the prior art using a lag-lead filter.
The PLL circuit shown in FIG. 11 includes a phase comparator 101, a charge pump circuit 102, a lag-lead filter 103, a low-pass filter 104, a voltage-controlled oscillator 105, and a frequency divider 106.
The phase comparator 101 compares phases of a reference signal φREF and an output signal NOUT of the frequency divider 106 and outputs an up signal /UP or a down signal DOWN corresponding to the result of comparison.
The charge pump circuit 102 receives the up signal /UP or down signal DOWN from the phase comparator 101 and outputs a charging and discharging current ICP to the lag-lead filter 3.
The lag-lead filter 103, for example, is comprised of a resistor RF1 and a capacitor CF1 connected in series between the output of the charge pump circuit 102 and the ground line. It receives the charging and discharging current ICP and outputs the generated voltage FIL of the series circuit to the low-pass filter 104.
The low-pass filter 104, for example, is comprised of a resistor RLP and a capacitor CLP connected in series between the output of the charge pump circuit 102 and the ground line. It receives the voltage FIL of the lag-lead filter 103 and outputs a voltage LPO of the capacitor CLP corresponding to the voltage FIL to the voltage-controlled oscillator 105.
The voltage-controlled oscillator 105 receives the output voltage LPO of the low-pass filter 104 and outputs a signal φVCO having a frequency corresponding to it.
The frequency divider 106 divides the output signal φVCO of the voltage-controlled oscillator 105 by a certain division ratio and outputs a signal NOUT to the phase comparator 101.
If the reference clock signal φREF is of a low frequency, for example, the horizontal synchronization signal HSYNC of 12 kHz or so, it becomes difficult to include the capacitor CF1 of the lag-lead filter 103 in a semiconductor chip, so it is preferable to make it an external part.
The grounding point of the voltage-controlled oscillator 105 included in a semiconductor chip and the grounding point of the external capacitor CF1 of the lag-lead filter 103 are different, so if the voltage FIL of the lag-lead filter 103 is directly used as a control voltage of the voltage-controlled oscillator 105, the potential difference of the two grounding points becomes noise superposed onto the control voltage when viewed from the voltage-controlled oscillator 105, whereby the jitter of the PLL circuit ends up being increased. Because of this, preferably a low-pass filter 104 built in the semiconductor chip is provided between the lag-lead filter 103 and the voltage-controlled oscillator 105. Since the grounding point of the capacitor CLP and the grounding point of the voltage-controlled oscillator 105 are from the same place, the aforesaid noise due to the potential difference of the two grounding points is reduced.
In the noise of the control voltage due to the potential difference between the grounding point of the external capacitor CF1 and the grounding point of the voltage-controlled oscillator 105, the noise voltage ΔVNOISE_LP output from the low-pass filter 104 is expressed as follows from the amplitude ΔVNOISE of the noise in the input of the low-pass filter 104, the time width NOISE of the noise, the frequency fNOISE of the noise, the shielding frequency fLP1 of the low-pass filter 104, and the time constant τLP1:                                                                         Δ                ⁢                                                                   ⁢                VNOISE_LP                            ≈                            ⁢                              Δ                ⁢                                                                   ⁢                                  VNOISE                  /                                      (                                          fNOISE                      /                      fLP1                                        )                                                                                                                          ≈                            ⁢                              Δ                ⁢                                                                   ⁢                VNOISE                ×                                  (                                      τ                    ⁢                                                                                   ⁢                                          NOISE                      /                      τ                                        ⁢                                                                                   ⁢                    LP1                                    )                                                                                        (        1        )            
For example, if the noise voltage ΔVNOISE is 10 mV, the time constant τNOISE is 2.8 nsec, and the time constant τLP1 is 280 nsec, the noise voltage ΔVNOISE_LP is about 100 μV.
FIGS. 12A to 12F give waveform diagrams for explaining the operation of the first mode of the PLL circuit of the prior art.
Waveform diagram of FIG. 12A shows the waveform of the reference clock signal φREF.
Waveform diagram of FIG. 12B shows the waveform of the output signal NOUT of the frequency divider 106.
Waveform diagram of FIG. 12C shows the waveform of the signal /UP of the phase comparator 101.
Waveform diagram of FIG. 12D shows the waveform of the signal DOWN of the phase comparator 101.
Waveform diagram of FIG. 12E shows the waveform of the output voltage FIL of the lag-lead filter 103.
Waveform diagram of FIG. 12F shows the waveform of the output voltage LPO of the low-pass filter 104.
The phase comparator 101 compares the timing of the rising edge of the reference clock signal φREF and the trailing edge of the output signal NOUT of the frequency divider 106. If the trailing edge of the signal NOUT is late relative to the rising edge of the reference clock signal φREF, a low level pulse signal, that is, the up signal /UP, is output. If the trailing edge of the signal NOUT is earlier, a high level pulse signal, that is, the down signal DOWN, is output.
The up signal /UP, for example, is input to the gate of a p-channel MOS transistor on the not shown power source line side of the charge pump circuit 102. By inputting a low level pulse signal to the up signal /UP, the p-channel MOS transistor is turned on, and the charging current ICP is supplied to the lag-lead filter 103.
In addition, the down signal DOWN, for example, is input to the gate of a n-channel MOS transistor on a not shown ground line side of the charge pump circuit 102. By inputting a high level pulse signal to the down signal DOWN, the n-channel MOS transistor is turned on, and the discharging current ICP is supplied to the lag-lead filter 103.
Due to the charging and discharging current ICP output from the charge pump circuit 102, the output voltage FIL of the lag-lead filter 103 and the output signal LPO of the low-pass filter 104 change. Due to this, the oscillation frequency of the voltage-controlled oscillator 105 increases or decreases.
In the period Δt when the up signal /UP or the down signal DOWN is generated, the output current ICP from the charge pump circuit 102 passes through the resistor RF1 of the lag-lead filter 103 and the resistor RLP of the low-pass filter 104 and charges or discharges the capacitor CF1 of the lag-lead filter 103 and the capacitor CLP of the low-pass filter 104. The output voltage FIL of the lag-lead filter 103 has a combined waveform of a rectangular voltage waveform S1LFIL generated by conducting the current ICP through the parallel resistance of the resistor RF1 and the resistor RLP and a flat waveform along the time axis generated by charging and discharging the parallel capacitance of the capacitor CF1 and the capacitor CLP and retaining the charge.
In the output voltage FIL of the lag-lead filter 103, if the resistor RF1 is sufficiently small compared with the resistor RLP and the capacitor CF1 is sufficiently large compared with the capacitor CLP, the voltage change ΔV1FIL of the voltage waveform S1FIL and the voltage change ΔV2FIL of the voltage waveform S2FIL are expressed as follows:                                                                         Δ                ⁢                                                                   ⁢                V1FIL                            =                            ⁢                              ICP                /                                  {                                                            (                                              1                        /                        RF1                                            )                                        +                                          (                                              1                        /                        RLP                                            )                                                        }                                                                                                        ≈                            ⁢                              ICP                ×                RF1                                                                        (        2        )                                                                                    Δ                ⁢                                                                   ⁢                V2FIL                            =                            ⁢                                                (                                      ICP                    ×                    Δ                    ⁢                                                                                   ⁢                    t                                    )                                /                                  (                                      CF1                    +                    CLP                                    )                                                                                                        ≈                            ⁢                                                (                                      ICP                    ×                    Δ                    ⁢                                                                                   ⁢                    t                                    )                                /                CF1                                                                        (        3        )            
Therefore, the output voltage FIL of the lag-lead filter 103 appears with almost the same waveform as that when there is no low-pass filter 104.
In addition, the area ZS1FIL of the voltage waveform S1LFIL and the area ZS2FIL of the voltage waveform S2FIL are expressed as follows:ZS1FIL=ΔV1FIL×Δt  (4)ZS2FIL=ΔV2FIL×T  (5)
Here, the sum of the area ZS1FIL and the area ZS2FIL (ZS1FIL+ZS2FIL) is related to the phase pull-in, and the area ZS2FIL is proportional to the voltage variation ΔV2FIL, so is related to the frequency change (pull-in). For example, if the frequency change is designed to be a half of the phase pull-in, the area ZS1FIL and the area ZS2FIL are substantially equal, so the following equation holds:
 ΔV2FIL≈ΔV1FIL×(Δt/T)  (6)
Since the time Δt is shorter than the period T, the voltage ΔV2FIL becomes smaller than the voltage ΔV1FIL.
The output voltage LPO of the low-pass filter 104 appears as a blunted waveform of the output voltage FIL of the lag-lead filter 103, but by treating the voltage waveform S1FIL and the voltage waveform S2FIL in the same way, the output voltage LPO can be separated into a voltage waveform S1LP corresponding to the rectangular voltage waveform S1FIL and a voltage waveform S2LP corresponding to the flat voltage waveform S2FIL for consideration.
The voltage waveform S1FIL has a blunted rising edge waveform changing exponentially by a time constant of the low-pass filter 104. The voltage ΔV1LPO rising exponentially from the voltage 0 to the voltage AV1FIL can be approximated by the following equation:                                                                                           Δ                  ⁢                                                                           ⁢                  V1LPO                  ⁢                                                                           ⁢                                      (                    t                    )                                                  =                                ⁢                                  Δ                  ⁢                                                                           ⁢                  V1FIL                  ×                                      {                                          1                      -                                              exp                        ⁡                                                  (                                                                                                                    -                                t                                                            /                              τ                                                        ⁢                                                                                                                   ⁢                            LP1                                                    )                                                                                      }                                                                                                                                            ≈                                    ⁢                                      Δ                    ⁢                                                                                   ⁢                    V1FIL                    ×                                          (                                                                        t                          /                          τ                                                ⁢                                                                                                   ⁢                        LP1                                            )                                                                      }                                                    ⁢                                  ⁢                  where          ,                                    τ              ⁢                                                           ⁢              LP1                        =                          CLP              ×              RLP                                                          (        7        )            
Therefore, if the time Δt is sufficiently shorter than the time constant τLP1 of the low-pass filter 104, the peak voltage ΔV1LPO is expressed by the following equation:ΔV1LPO≈ΔV1FIL×(Δt/τLP1)  (8)
On the other hand, the falling waveform of the voltage waveform S1LP which falls exponentially from the peak voltage ΔV1LPO to the voltage ΔV2FIL can be approximated by the following equation:                                                                                                               Δ                    ⁢                                                                                   ⁢                    V1LPO                    ⁢                                                                                   ⁢                                          (                      t                      )                                                        =                                    ⁢                                                                                    (                                                                              Δ                            ⁢                                                                                                                   ⁢                            V1LPO                                                    -                                                      Δ                            ⁢                                                                                                                   ⁢                            V2FIL                                                                          )                                            ×                                              exp                        ⁡                                                  (                                                                                                                    -                                t                                                            /                              τ                                                        ⁢                                                                                                                   ⁢                            LP2                                                    )                                                                                      +                                          Δ                      ⁢                                                                                           ⁢                      V2FIL                                                                                                                                            ≈                                    ⁢                                      Δ                    ⁢                                                                                   ⁢                    V1LPO                    ×                                          exp                      ⁡                                              (                                                                                                            -                              t                                                        /                            τ                                                    ⁢                                                                                                           ⁢                          LP2                                                )                                                                                                                          ⁢                                          ⁢                      where            ,                          T1p2              ≈                              CLP                ×                                                      (                                          RLP                      +                      RF1                                        )                                    .                                                                    ⁢                                                       (        9        )            
In addition, at the trailing edge of the reference clock signal φREF, namely, the time t=αT (α≈ 1/10), the voltage after the blunted voltage waveform S1LP has exponentially attenuated can be expressed by the following equation:                                                                         Δ                ⁢                                                                   ⁢                V1LPO                ⁢                                  (                                      α                    ⁢                                                                                   ⁢                    T                                    )                                            ≈                            ⁢                              Δ                ⁢                                                                   ⁢                V1LPO                ×                                  exp                  ⁡                                      (                                                                  -                        α                                            ⁢                                                                                           ⁢                                              T                        /                        τ                                            ⁢                                                                                           ⁢                      LP2                                        )                                                                                                                          ≈                            ⁢                              Δ                ⁢                                                                   ⁢                V1FIL                ×                                  (                                      Δ                    ⁢                                                                                   ⁢                                          t                      /                      τ                                        ⁢                                                                                   ⁢                    LP1                                    )                                ×                                  exp                  ⁡                                      (                                                                  -                        α                                            ⁢                                                                                           ⁢                                              T                        /                        τ                                            ⁢                                                                                           ⁢                      LP2                                        )                                                                                                          (        10        )            
For displaying pictures or texts, at the trailing edge of the reference clock signal φREF, namely, at the left end of the screen, the voltage waveform S1LP must be sufficiently attenuated. Therefore, it is a criterion of design that the following equation be satisfied:
 ΔV1LPO(αT)≦ΔV2FIL  (11)
Entering equation (10) and equation (6) into equation (11) to modify it, the following equation is obtained:T/τLP1≦exp(αt/τLP2)  (12)
From equation (12), if α= 1/10, the next equation holds:τLP1≈τLP2≦35.8  (13)
For example,
if T=64 μsec, τLP1≦1.8 μsec
if T=10 μsec, τLP1≦280 nsec
From equation (1), in order to make the value of the noise voltage ΔVNOISE_LP small, it is necessary to increase the value of the time constant τLP1 to some extent. In this case, however, it becomes difficult to satisfy equation (11).
That is, if the time constant τLP1 of the low-pass filter 104 is increased to reduce the influence of the noise, the control voltage continues changing even after the trailing edge of the reference clock signal φREF, so there arises a problem that the effect of the phase correction performed at the trailing edge of the reference clock signal φREF ends up being reduced.
Note that if the time constant τLP1 is sufficiently smaller than the period T, the area of the blunted voltage waveform S1LP is roughly given by the following equation:                                                                         S                                  1                  ⁢                  LP                                            ≈                            ⁢                                                                    Δ                    ⁢                                                                                   ⁢                                          V                                              1                        ⁢                        LPO                                                              ×                    Δ                    ⁢                                                                                   ⁢                    t                                    2                                +                                  Δ                  ⁢                                                                           ⁢                                      V                                          1                      ⁢                      LPO                                                        ⁢                                                            ∫                                              t                        =                        0                                                                    t                        =                        T                                                              ⁢                                                                  exp                        ⁡                                                  (                                                                                                                    -                                t                                                            /                              τ                                                        ⁢                                                                                                                   ⁢                            LP2                                                    )                                                                    ⁢                                              ⅆ                        t                                                                                                                                                                    ≈                            ⁢                              ICP                ×                RF1                ×                Δ                ⁢                                                                   ⁢                t                                                                        (        14        )            
From the above equation, it is clear that the area of the blunted voltage waveform S1LP coincides with the area of the rectangular lead pulse of the lag-lead filter when there is no low-pass filter 104.
Next, an explanation will be made of a second mode of the PLL circuit of the prior art using a lag-lead filter.
FIG. 13 is a view of the configuration of the second mode of a PLL circuit of the prior art using a lag-lead filter.
The same reference numerals in FIG. 11 and FIG. 13 indicate the same constituent elements. In addition, the PLL circuit shown in FIG. 13 includes a bias circuit 107, a capacitor GPB, and a capacitor CNB.
The difference of the second mode relative to the first mode lies in the point that a bias circuit 107 is incorporated instead of a low-pass filter 104 between the lag-lead filter 103 and the voltage-controlled oscillator 105.
The bias circuit 107 receives the output voltage FIL of the lag-lead filter 103, generates a bias voltage NBIAS and a bias voltage PBIAS, and outputs them to the voltage-controlled oscillator 105. The bias circuit, for example, is comprised of a combination of current mirror circuits.
Here, the bias circuit 107 and the voltage-controlled oscillator 105 will be explained.
FIG. 15 is a view of an example of a circuit of a voltage-controlled oscillator.
The voltage-controlled oscillator shown in FIG. 15 comprises delay blocks 51-1 to 51-n and an NAND circuit 56.
In addition, each of the delay blocks 51-1 to 51-n has a two-stage inverter type delay stage comprised of a pMOS transistor Qp50, a pMOS transistor Qp51, a nMOS transistor Qn50, and a nMOS transistor Qn51 and has an output buffer BUF.
The pMOS transistor Qp51 and the nMOS transistor Qn50 receive as input a signal from the earlier stage at their mutually connected gates and output a signal to the next stage from their mutually connected drains. The source of the pMOS transistor Qp51 is connected to the power line Vdd through the drain and source of the pMOS transistor Qp50, while the source of the nMOS transistor Qn50 is connected to the ground line through the drain and source of the nMOS transistor Qn51. A bias voltage PBIAS is applied to the gate of the pMOS transistor Qp50, while a bias voltage NBIAS is applied to the gate of the nMOS transistor Qp51.
In each delay block, two inverter type stages are connected in cascade. A buffer BUF is inserted at the output of the delay block.
As shown in the circuit example of FIG. 15, each delay block included in the voltage-controlled oscillator 105, for example, comprises two inverter type delay stages each provided with a current source transistor (the PMOS transistor Qp50) on the power line side controlled by the bias voltage PBIAS and a current source transistor (the nMOS transistor Qp51) on the ground line side controlled by the bias voltage NBIAS and one inverter (output buffer BUF) for use as a buffer.
If the signal PWON is set at a high level, the gate of the NAND circuit 56 is turned ON, a signal from the last stage of the delay blocks connected in cascade is fed back to the first stage, and oscillation starts. At this time, clock signals φ{0} to φ{π} are output from the delay blocks.
FIG. 16 is a circuit diagram showing an example of a bias circuit.
The bias circuit shown in FIG. 16 comprises a pMOS transistor Qp101, a pMOS transistor Qp102, an nMOS transistor Qn101, and an nMOS transistor Qn102.
The nMOS transistor Qn101 receives a voltage FIL at its gate, is connected to the ground line at its source, and is connected to the drain of the pMOS transistor Qp101 at its drain.
The pMOS transistor Qp101 is connected to the power line Vdd at its source, is connected to its own drain at its gate, and outputs the bias voltage PBIAS from its gate.
The nMOS transistor Qn102 receives the bias voltage PBIAS at its gate, is connected to the power line Vdd at its source, and is connected to the drain of the nMOS transistor Qn102 at its drain.
The nMOS transistor Qn102 is connected to the ground line Vdd at its source, is connected to its own drain at its gate, and outputs the bias voltage NBIAS from its gate.
The current mirror type bias circuit shown in FIG. 16, for example, generates a bias voltage PBIAS by the first current mirror circuit (the nMOS transistor Qn101 and the pMOS transistor Qp101) to which the voltage FIL is input and furthermore generates a bias voltage NBIAS by the second current mirror circuit (the pMOS transistor Qp102 and the nMOS transistor Qn102) to which the bias voltage PBIAS is input.
By supplying the voltage-controlled oscillator 105 with the bias voltages generated by the bias circuit shown in FIG. 16, even if the output voltage FIL of the lag-lead filter 103 changes, the current flowing to the current source transistor of the power line side (the PMOS transistor Qp50) controlled according to the bias voltage PBIAS and the current flowing to the current source transistor of the ground line side (the nMOS transistor Qn51) controlled according to the bias voltage NBIAS are controlled to generally balance out. In addition, under standard conditions, the delay time of each inverter type delay stage at the rising edge of output and the delay time at the trailing edge of output change in the same way to balance each other even if the voltage FIL changes somewhat. Furthermore, for the inverter for buffer use, the ratio of sizes of the pMOS and nMOS transistors is decided in order to balance the delay time at the rising edge and the delay time at the trailing edge. Consequently, the fluctuation of the duty of clock signals output from the voltage-controlled oscillator 105 caused by a change of the voltage FIL, variability in the processes, and a change of the power voltage can be prevented.
However, when a large consumed power is injected into the above bias circuit 107, the overall power consumption of the PLL circuit ends up being increasingly increased, so usually the power consumption of the bias circuit 107 has to be kept lower than the power consumption of the voltage-controlled oscillator 105. Due to this, the values of the output impedance RNBO and RPBO of the bias circuit 107 need be relatively large.
On the other hand, when the voltage-controlled oscillator is in operation, changes of the output voltages of all delay stages are propagated via the gate capacitance of the current power transistors or the branch transistors included in the delay stages into which the bias voltage NBIAS and the bias voltage PBIAS are input. As a result, when the output impedance RNBO and output impedance RPBO of the bias circuit are relatively large in value, the characteristic of the oscillation frequency vs. control voltage of the voltage-controlled oscillator ends up deviating and the output of the bias circuit ends up losing out to the noise in some cases (see Japanese Unexamined Patent Publication (Kokai) No. 11-27106, “Voltage-Controlled Oscillation Circuit”.)
In order to prevent such a problem without increasing the power consumption, as shown in FIG. 13, the practice has been to provide a capacitor CNP or capacitor CPB between the output of the bias circuit 107 and the power line or the ground line to stabilize the bias voltage NBIAS or the bias voltage PBIAS.
Assuming that the voltage under the gate of the current source transistor changes due to the drain voltage of the current source transistor changing up to an intermediate voltage, namely, changing by exactly the power voltage Vdd/2, when the delay stages are operating, when no capacitor for stabilization is provided, the oscillation voltage ΔVOSC superposed on the gate voltage can be expressed by the following equation from the gate capacitance Cg of the current source transistors included in the delay stages of the voltage-controlled oscillator 105 and the number N of the delay stages:                                                                         Δ                ⁢                                                                   ⁢                V0SC                            ≈                            ⁢                                                {                                                            (                                              Cg                        /                        2                                            )                                        /                                          (                                              N                        ×                        Cg                                            )                                                        }                                ×                                  (                                      Vdd                    /                    2                                    )                                                                                                        ≈                            ⁢                                                Vdd                  /                  4                                ⁢                N                                                                        (        15        )            
For example, if the power voltage Vdd is 3.3V and the number N of the delay stages is 17, the oscillation voltage ΔVOSC superposed on the gate voltage becomes about 50 mV. This value is roughly three orders of magnitude larger than the accuracy required by the control voltage of the voltage-controlled oscillator 105.
In addition, if the capacitor CBO is provided for stabilization of the control voltage, the equation becomes as follows:                                                                         Δ                ⁢                                                                   ⁢                V0SC                            ≈                            ⁢                                                {                                                            (                                              Cg                        /                        2                                            )                                        /                                          (                                                                        N                          ×                          Cg                                                +                        CBO                                            )                                                        }                                ×                                  (                                      Vdd                    /                    2                                    )                                                                                                        ≈                            ⁢                                                (                                                            Cg                      /                      4                                        ⁢                    CBO                                    )                                ×                Vdd                                                                        (        16        )            
As the gate capacitance Cg is several tens of fF, if the capacitor CBO is made 10 pF or so, the oscillation voltage ΔVOSC becomes a few hundred μV and is reduced to a value one order of magnitude larger than the accuracy sought for the control voltage of the voltage-controlled oscillator 105.
FIG. 14 gives waveform diagrams for explaining the operation of the second mode of the PLL circuit of the prior art.
Waveform diagram of FIG. 14A shows the waveform of the reference clock signal φREF.
Waveform diagram of FIG. 14B shows the waveform of the output signal NOUT of the frequency divider 106.
Waveform diagram of FIG. 14C shows the waveform of the up signal /UP of the phase comparator 101.
Waveform diagram FIG. 14D shows the waveform of the down signal DOWN of the phase comparator 101.
Waveform diagram (E) of FIG. 14 shows the waveform of the output voltage FIL of the lag-lead filter 103.
Waveform diagram (F) of FIG. 14 shows the waveform of the bias voltage PBIAS.
Waveform diagram (G) of FIG. 14 shows the waveform of the bias voltage NBIAS.
In the time Δt when the up signal /UP or the down signal DOWN is generated, the output current ICP from the charge pump circuit 102 passes through the resistor RF1 of the lag-lead filter 103 and charges or discharges the capacitor CF1 of the lag-lead filter 103. In the output voltage FIL of the lag-lead filter 103, a rectangular pulse voltage waveform S1 is generated due to the current ICP flowing through the resistor RF1, while a flat waveform voltage S2 is generated along the time axis due to the charging and discharging and retaining of the charge ICP×Δt in the capacitor CF1.
The voltage change ΔV1 of the voltage waveform S1 and the voltage change ΔV2 of the voltage waveform S2 in the output voltage FIL of the lag-lead filter 103 are expressed by the following equations:ΔV1=ICP×RF1  (17)ΔV2=(ICP×Δt)/CF1  (18)
In addition, the area ZS1 of the voltage waveform S1 and the area ZS2 of the voltage waveform S2 are expressed by the following equations:ZS1=ΔV1×Δt  (19)ZS2≈ΔV2×T  (20)
Here, the sum of the area ZS1 and the area ZS2 (ZS1+ZS2) is related to the phase pull-in, and the area ZS2 is related to the frequency change (pull-in). For example, if the frequency change is designed to be a half of the phase pull-in, since the area ZS1FIL and the area ZS2FIL are substantially equal, the following equation holds:ΔV2≈ΔV1×(Δt/T)  (21)
Since the time Δt is shorter than the period T, the voltage ΔV2 becomes sufficiently smaller than the voltage ΔV1.
The output of the bias circuit 107, that is, the bias voltage NBIAS, is generated as a blunted rectangular waveform S1NB and a flat waveform S2NB. The voltage waveform S1NB is the rectangular pulse waveform of the voltage FIL blunted by the capacitor CNB and changes exponentially with a time constant determined by the output resistor RNBO of the bias circuit 107 and the capacitor CNB for voltage stabilization. The voltage waveform S2NB is a waveform corresponding to the voltage waveform S2.
Here, for simplifying the explanation, the case in which the gain of the bias circuit 107 is 1 will be explained. The rising edge of the exponentially changing blunted pulse voltage waveform S1NB can be approximated by the following equation:                                                                                                               Δ                    ⁢                                                                                   ⁢                                          V1NB                      ⁡                                              (                        t                        )                                                                              =                                    ⁢                                      Δ                    ⁢                                                                                   ⁢                    V1                    ×                                          {                                              1                        -                                                  exp                          ⁡                                                      (                                                                                                                            -                                  t                                                                /                                τ                                                            ⁢                                                                                                                           ⁢                              NB                                                        )                                                                                              }                                                                                                                                            ≈                                    ⁢                                      Δ                    ⁢                                                                                   ⁢                    V1                    ×                                          (                                                                        t                          /                          τ                                                ⁢                                                                                                   ⁢                        NB                                            )                                                                                                    ⁢                                          ⁢                      where            ,                                                   ⁢                                          τ                ⁢                NB                            =                              CNB                ×                RNBO                                                    ⁢                                                       (        22        )            
Therefore, the peak voltage ΔV1NB can be expressed by the following equation:ΔV1NB≈ΔV1×(Δt/τNB)  (23)
On the other hand, the falling waveform of the blunted voltage waveform S1NB can be approximated by the following equation:                                                                         Δ                ⁢                                                                   ⁢                V1NB                ⁢                                                                   ⁢                                  (                  t                  )                                            =                            ⁢                                                                    (                                                                  Δ                        ⁢                                                                                                   ⁢                        V1NB                                            -                                              Δ                        ⁢                                                                                                   ⁢                        V2                                                              )                                    ×                                      exp                    ⁡                                          (                                                                                                    -                            t                                                    /                          τ                                                ⁢                                                                                                   ⁢                        NB                                            )                                                                      +                                  Δ                  ⁢                                                                           ⁢                  V2                                                                                                        ≈                            ⁢                              Δ                ⁢                                                                   ⁢                V1NB                ×                                  exp                  ⁡                                      (                                                                                            -                          t                                                /                        τ                                            ⁢                                                                                           ⁢                      NB                                        )                                                                                                          (        24        )            
At the trailing edge of the reference clock signal φREF, namely, at the time t=αT (≈T/10), the voltage at which the voltage waveform S1NB has exponentially attenuated can be expressed by the following equation:                               Δ          ⁢                                           ⁢                      V1NB            ⁡                          (                              α                ⁢                                                                   ⁢                T                            )                                      ≈                  Δ          ⁢                                           ⁢          V1NB          ×          exp          ⁢                      {                                                            -                                      (                                          α                      ⁢                                                                                           ⁢                      T                                        )                                                  /                τ                            ⁢                                                           ⁢              NB                        }                          ≈                  Δ          ⁢                                           ⁢          V1          ×                      (                          Δ              ⁢                                                           ⁢                              t                /                τ                            ⁢                                                           ⁢              NB                        )                    ×          exp          ⁢                      {                                                            -                                      (                                          α                      ⁢                                                                                           ⁢                      T                                        )                                                  /                τ                            ⁢                                                           ⁢              NB                        }                                              (        25        )            
For displaying pictures or text, at the trailing edge of the reference clock signal φREF, namely, at the left end of the screen, the voltage waveform S1NB must be sufficiently attenuated, so it is a criterion of design that the following equation be satisfied:ΔV1NB(αT)≦ΔV2  (26)
Entering equation (25) and equation (21) into equation (26) to modify it, the following equation is obtained:T/τNB≦exp(αT/τNB)  (27)
Therefore, the same equation as equation (12) of the first mode can be obtained. If α= 1/10, the next equation holds:τNB≦T/35.8  (28)
However, when the bias voltage NBIAS and the bias voltage PBIAS are generated in the bias circuit 107 as in the second mode, a frequent practice is to receive one bias voltage and generate the other bias voltage as shown in the circuit example of FIG. 16. The waveform diagram of FIG. 14 is of the case where the bias voltage NBIAS is received and the bias voltage PBIAS is generated.
In this case, the waveform of the bias voltage PBIAS has a combined waveform of a further blunted voltage waveform S1PB generated by inverting the blunted pulse waveform S1NB of the bias voltage NBIAS and a flat voltage waveform S2PNB corresponding to the flat voltage waveform S2NB of the bias voltage NBIAS.
Here, for facilitating understanding of the explanation, the following explanation is given assuming the bias voltage PBIAS is not inverted and switching the terms “rising edge” and “trailing edge”.
The rising edge of the exponentially changing strongly blunted waveform S1PB first rises up toward the peak voltage ΔV1NB of the bias voltage NBIAS, so can be approximated by the following equation:|ΔV1PB(t)|≈ΔV1NB×{1−exp(−t/τPB1)}  (29)where, τPB1=CPB×RPBO.
However, since the voltage of the bias voltage NBIAS decreases gradually, the voltage change of the bias voltage PBIAS gradually levels off. When the time constant τNB≈τPB1, the bias voltage NBIAS and the bias voltage PBIAS cross near the time t≈τNB. At this time, the bias voltage PBIAS becomes the peak voltage ΔV1NB. Namely, near the time t≈τNB, the voltage ΔV1NB (τNB)=ΔV1NB(0)/e, so the voltage change ΔV1PB of the bias voltage PBIAS can be expressed by the following equation:|ΔV1PB(t)|≈ΔV1NB/e  (30)
The voltage waveform S1PB at the time when the bias voltage PBIAS starts to decrease from the peak can be roughly approximated by the following equation:                                                                                                                                 Δ                    ⁢                                                                                   ⁢                                          V1PB                      ⁡                                              (                        t                        )                                                                                                              ≈                                ⁢                                                                                                Δ                      ⁢                                                                                           ⁢                      V1PB                                                                            ×                  exp                  ⁢                                      {                                                                                            -                                                      (                                                          t                              -                                                              τ                                ⁢                                                                                                                                   ⁢                                PB2                                                                                      )                                                                          /                        τ                                            ⁢                                                                                           ⁢                      PB2                                        }                                                                                                                          ≈                                ⁢                                  Δ                  ⁢                                                                           ⁢                  V1NB                  ×                                      exp                    ⁡                                          (                                                                                                    -                            t                                                    /                          τ                                                ⁢                                                                                                   ⁢                        PB2                                            )                                                                                                          ⁢                                  ⁢                  where          ,                                    τ              ⁢                                                           ⁢              PB2                        ≈                                          e                            ×              τ              ⁢                                                           ⁢              PB1                        ≈                                          e                            ×              CPB              ×              RPBO                                                          (        31        )            
Furthermore, the waveform of the portion of the voltage waveform S1PB after removal of the tail can be roughly approximated by the following equation:                                                                                                           Δ                  ⁢                                                                           ⁢                                      V1PB                    ⁡                                          (                      t                      )                                                                                                  ≈                            ⁢                              Δ                ⁢                                                                   ⁢                V1NB                ×                                  [                                                            exp                      ⁡                                              (                                                                                                            -                              t                                                        /                            τ                                                    ⁢                                                                                                           ⁢                          NB                                                )                                                              +                                                                                                                                        ⁢                              exp                ⁢                                  {                                                            -                      t                                        /                                                                  (                                                                              τ                            ⁢                                                                                                                   ⁢                                                          NB                              2                                                                                +                                                      τ                            ⁢                                                                                                                   ⁢                                                          PB1                              2                                                                                                      )                                                                              }                                            ]                                                                          ≈                            ⁢                              Δ                ⁢                                                                   ⁢                V1NB                ×                                  [                                                            exp                      ⁡                                              (                                                                                                            -                              t                                                        /                            τ                                                    ⁢                                                                                                           ⁢                          NB                                                )                                                              +                                                                                                                                        ⁢                              exp                ⁢                                  {                                                            -                      t                                        /                                          (                                                                        2                                                ×                        τ                        ⁢                                                                                                   ⁢                        PB1                                            )                                                        }                                            ]                                                          (        32        )            
For displaying pictures or text, at the trailing edge of the reference clock signal φREF, namely, at the left end of the screen, the strongly blunted voltage S1PB must be sufficiently attenuated, so it is a criterion of design that the following equation be satisfied:ΔV1PB(αT)≦ΔV2  (33)
By assuming the time constant τNB≈τPB1≈τB0 and entering equation (32) and equation (21) into equation (33) to modify it, the following equation is obtained:                                           T            /            τ                    ⁢                                           ⁢          BO                ≤                  1          /                      [                                          exp                ⁡                                  (                                                            -                      α                                        ⁢                                                                                   ⁢                                          T                      /                      τ                                        ⁢                                                                                   ⁢                    BO                                    )                                            +                              exp                ⁢                                  {                                                            -                      α                                        ⁢                                                                                   ⁢                                          T                      /                                              (                                                                              2                                                    ×                          τ                          ⁢                                                                                                           ⁢                          BO                                                )                                                                              }                                                      ]                                              (        34        )            
Therefore, the same equation as equation (12) of the first mode can be obtained. When α= 1/10, the next equation holds:τBO≦T/60.2  (35)
In equation (35), for example,
if T=64 μsec, τBO≦1.06 μsec
if T=10 μsec, τBO≦166 nsec
If the value of the output resistor RNB0 or the output resistor RPB0 of the bias circuit 107 is set large to reduce the power consumption of the bias circuit 107, the value of the time constant τB0 also becomes larger and it becomes difficult to satisfy equation (33). That is, the bias voltage continues changing even after the trailing edge of the reference clock signal φREF, so there arises a problem that the effect of the phase correction performed at the trailing edge of the reference clock signal φREF ends up being reduced.
Under standard condition, designing the circuit to satisfy equation (11) or equation (33) does not pose that much of a problem, but if considering the power voltage or temperature and the variability in processes, it is necessary to further secure, for example, approximately a 200% margin. This is not easy. In addition, although not shown, when both the low-pass filter 104 and the bias circuit 107 cause double blunting of the input voltage waveform of the voltage-controlled oscillator 105, needless to say the above problem becomes more severe.